From Academic Kids

Missing image
A PDP-8 on display at the Smithsonian's National Museum of American History in Washington, D.C.. This example is from the first generation of PDP-8s, built with discrete transistors and later known as the Straight 8.

The PDP-8 was the first successful commercial minicomputer, produced by Digital Equipment Corporation (DEC) in the 1960s. It was the first widely-sold computer in the DEC PDP series of computers (the PDP-5 was not originally intended to be a general-purpose computer).



The PDP-8 was a 12-bit computer. In its basic configuration it had a main memory of 4,096 twelve-bit words (that is, 4K words, equivalent to 6 kilobytes), expandable to 32,768 words (32K words / 48 KB). At its inception, the PDP-8 had only eight instructions and two registers (a 12-bit accumulator, AC, and a single-bit "link register", L). The machine used a magnetic core memory system that operated at a cycle time of 1.5 microseconds, so that a typical two-cycle (Fetch, Execute) memory-reference instruction ran at a speed of 0.333 MIPS. Later machines added a second register (the "MQ" Multiplier/Quotient Register), actual multiply and divide instruction options, and faster operation.

The PDP-8 was an historically important computer because of the advances in technology, I/O, software development, and operating system design that occurred during its reign.

The earliest PDP-8 model (the so-called "Straight-8") used discrete transistor technology and was approximately the size of a compact refrigerator. This was followed by the PDP-8/S. By using a one-bit serial ALU implementation, it was smaller and less-expensive but vastly slower than the original PDP-8. Intermediate systems (the PDP-8/I and /L, the PDP-8/E, /F, and /M, and the PDP-8/A) returned to a fully-parallel implementation and used TTL MSI logic. The last revisions of PDP-8 models used single custom CMOS microprocessors. There was never a historical "system on a chip". However, in recent years enthusiasts have created entire PDP-8 systems using single FPGA devices. (This is possible because an entire PDP-8, its main memory system, and its I/O equipment is collectively much less complex than even the cache memories used in most modern microprocessors.)


The I/O systems underwent huge changes during the PDP-8 era. Early PDP-8 models used a front-panel interface, a paper-tape reader and a teletype printer with an optional paper-tape punch. Over time I/O systems such as magnetic tape, RS-232 and current loop dumb terminals, punched card readers, and fixed-head disks were added. Toward the end of the PDP-8 era, floppy disks and moving-head cartridge disk drives were popular I/O devices. Modern enthusiasts have created standard PC style IDE hard disk adapters for real and simulated PDP-8 computers.

I/O was supported through several different methods:

  • In-backplane dedicated slots for I/O controllers
  • A "Negative" I/O bus (using negative voltage signalling)
  • A "Positive" I/O bus (the same architecture using TTL signalling)
  • The Omnibus (a backplane of undedicated slots)

A rudimentary form of DMA called "three-cycle data break" was supported; this required the assistance of the processor. Essentially, "data break" moved some of common logic (needed to implement the I/O device) from each I/O device into one common copy of the logic within the processor, placing the processor in charge of maintaining the DMA address and word count registers. In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word. By the time the PDP-8/E was introduced, this logic had become cheap and "one-cycle data break" became more popular, moving back to the individual I/O devices all the responsibility for maintaining the word count and transfer address registers; this effectively tripled the DMA transfer rate because only the target data needed to be transferred to/from the core memory.

Programming facilities

Software development systems for the PDP-8 series began with the most basic front panel entry of raw binary machine code. In the middle era, PAL-8 assembly language source code was often stored on paper tape, read into memory, and saved to paper tape, and later assembled from paper tape into memory. Toward the end of the PDP-8 era, operating systems such as OS/8 and COS-310 allowed a traditional line-mode editor and command-line compiler development system using languages such as PAL-III assembly language, FORTRAN, BASIC, and DIBOL.

Early PDP-8 systems did not have an operating system, just a front panel and run and halt switches. Various papertape "operating systems" were developed, as were single user disk operating systems. Toward the end of the PDP-8 era, fairly modern and advanced RTOS and preemptive multitasking multi-user systems were available: a real-time system (RTS-8) was available as were multiuser commercial systems (COS-300 and COS-310) and a dedicated single-user word-processing system (WPS-8).

Instruction set

Basic instructions:

000 - AND - AND the memory operand with AC.
001 - TAD - Twos-complement ADd the memory operand to <L,AC> (a 13 bit value).
010 - ISZ - Increment the memory operand and Skip next instruction if result is Zero.
011 - DCA - Deposit AC into the memory operand and Clear AC.
100 - JMS - JuMp to Subroutine (storing return address in first word of subroutine!).
101 - JMP - JuMP.
110 - IOT - Input/Output Transfer.
111 - OPR - microcoded OPeRations (on/using the accumuator, link, and MQ registers).

A wide variety of operations are available through the OPR microcoded instructions including most of the conditional branch (skip) instructions. In general, the operations within each Group can be combined by OR'ing the bit patterns for the desired operations into a single instruction. If none of the bits are set, the result is the NOP instruction.

Group 1 operations:

CLA - clear AC
CLL - clear the L bit
CMA - ones complement AC
CML - complement L bit
IAC - increment <L,AC>
RAR - rotate <L,AC> right
RAL - rotate <L,AC> left
RTR - rotate <L,AC> right twice
RTL - rotate <L,AC> left twice

Group 2 operations:

SMA - skip on AC < 0 (or group)
SZA - skip on AC = 0 (or group)
SNL - skip on L /= 0 (or group)
SKP - skip unconditionally
SPA - skip on AC >= 0 (and group)
SNA - skip on AC /= 0 (and group)
SZL - skip on L = 0 (and group)
CLA - clear AC
OSR - or switches with AC
HLT - halt

Example program

Here is an example of a complete PDP-8 assembly language program: "Hello, world!" written for the PAL-III assembler.

/ adapted from example in Digital PDP-8 Handbook Series, Introduction to Programming, p5-12
   *200                / set assembly origin (load address)
   hello,  cla cll
           tls         / tls to set printer flag.
           tad charac  / set up index register
           dca ir1     / for getting characters.
           tad m6      / set up counter for
           dca count   / typing characters.
   next,   tad i ir1   / get a character.
           jms type    / type it.
           isz count   / done yet?
           jmp next    / no: type another.
   type,   0           / type subroutine
           jmp .-1
           jmp i type
   charac, .           / used as initial value of ir1
           310 / H
           305 / E
           314 / L
           314 / L
           317 / O
           254 / ,
           240 /
           327 / W
           317 / O
           322 / R
           314 / L
           304 / D
           241 / !
   m6,     -15
   count,  0
   ir1 = 10

Subroutines on the PDP-8

The PDP-8 did not implement any general-purpose stack so there was no stack upon which to store the PC, AC, or any other context when a subroutine was called or an interrupt occurred. Instead, the updated PC simply replaced the first word of the targeted subroutine. An indirect JMP instruction was then used to exit from the subroutine.

For example, here is "Hello, World!" re-written to use a subroutine:

   *200                    / Set assembly origin (load address)

   HELLO,  CLA CLL         / Clear the AC and the Link bit
           TAD (DATA-1)    / Point AC just *BEFORE* the data (accounting for later pre-increment behavior)
           DCA 10          / Put that into one of ten auto-pre-increment memory locations
   LOOP,   TAD I 10        / Pre-increment mem location 10, fetch indirect to get the next character of our message
           SNA             / Skip on non-zero AC
           HLT             / Else halt at end of message
           JMS OUT1        / Write out one character
           JMP LOOP        / And loop back for more

   OUT1,   0               / Will be replaced by caller's updated PC
           TSF             / Skip if printer ready
           JMP .-1         / Wait for flag
           TLS             / Send the character in the AC
           CLA CLL         / Clear AC and Link for next pass
           JMP I OUT1      / Return to caller

   DATA,  "H               / A well-known message
          "e               /
          "l               / NOTE:
          "l               /
          "o               /   Strings in PAL-8 and PAL-III were "sixbit"
          ",               /   To use ASCII, we'll have to spell that out, character by character
          "                /
          "w               /
          "o               /
          "r               /
          "l               /
          "d               /
          "!               /
          015              /
          012              /
          0                / Mark the end of our .ASCIZ string ('cause .ASCIZ hadn't been invented yet!)

This dedicated storage for the return address made the use of reentrancy and recursion difficult because the programmer would have needed to explicitly store away the return address onto a programmer-maintained stack. It also made it difficult to use ROM with the PDP-8 because read-write return-address storage was comingled with read-only code storage in the address space. Programs intended to be placed into ROMs approached this problem in several ways:

  • They avoided the use subroutines,
  • They copied themselves to core memory before execution, or
  • They were placed into special ROM cards that provided a few words of read/write memory, accessed indirectly through the use of a thirteenth flag bit in each ROM word.


There was a single interrupt line on the PDP-8 I/O bus and interrupts were processed identically to having called a subroutine at location 0000 except that the interrupt system was also automatically disabled. Just as it was difficult to reentrantly call subroutines, it was difficult to nest interrupts and this was usually not done; each interrupt ran to completion and re-enabled the interrupt system just before executing the JMP I 0 instruction which acted as the exit from the interrupt.

Because there was only a single interrupt line on the I/O bus, the occurence of an interrupt conveyed no information to the processor about the source of the interrupt. Instead, the interrupt service routine had to serially poll each active I/O device to see if it was the source of the interrupt; the code that did this was usually referred to as a skip chain because it consisted of a lot of PDP-8 "test and skip if flag set" I/O instructions. (It was also not unheard-of for a skip chain to reach its end and not have found any device in need of service.) The relative interrupt priority of the I/O devices was determined by their position in the skip chain with devices nearer the front of the skip chain having higher priority for service.

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